Generally, shallow trench isolations (STIs) are used to separate and isolate active areas, such as transistors and photo diodes, on a semiconductor wafer from each other. The STIs are formed by etching trenches, forming silicon oxide liners in the trenches, overfilling the trenches with a dielectric such as an oxide, and then removing any excess dielectric outside the trenches. This dielectric helps to electrically isolate the active areas from each other. For fabricating a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) which has a low tolerance for the leakage of signal between photodiodes, a field implantation is further used after the formation of silicon oxide liners. In the overfilling operation, high-density plasma (HDP) chemical vapor deposition (CVD) is typically used for filling a HDP oxide in the trenches. However, the field implantation and the HDP CVD, as well as the trench etching, often cause plasma damages to sidewalls and bottoms of the trenches. Such plasma damages are the sources resulting in dark current, which is the cause of the “white pixel” defect in a CIS.